CACHE SIMULATOR
In this project, I created a cache simulator that simulates the behavior of a computer's cache system. The process that is being performed is filling the pixels of a fractal image. I have implemented different caches, such as the fully associative cache, direct mapped cache, N-way set associative cache, and a hierarchy of L1-L2-L3 N-way set associative caches. The caches support read/write functions, and these functions are used to read/write data for the fractal being drawn (reading a single byte and writing a single byte).
My cache simulator supports reading/writing different data types such as a short, int and long (16- and 32- bits). I have also experimented with 5 eviction policies: R (Random), RR (Round Robin), LRU (Least Recently Used), MRU (Most Recently Used) and LFU (Least Frequently Used).
My cache simulator supports reading/writing different data types such as a short, int and long (16- and 32- bits). I have also experimented with 5 eviction policies: R (Random), RR (Round Robin), LRU (Least Recently Used), MRU (Most Recently Used) and LFU (Least Frequently Used).
In addition, I implemented real-time interactive visualizations for the different cache levels. These show hit/miss and cost increases with time. Using the 32-way cache with RR as the eviction policy, the increase in efficiency from the Fully Associative Cache is around 95%.